The present invention relates to a method and/or architecture for a master/slave processor memory generally and, more particularly, to a method and/or architecture for a master/slave processor memory with inter-accessability in an integrated embedded system.
Conventional embedded systems can contain two or more identical processors. Such systems typically dedicate N-1 slave processors to specific tasks, while the Nth processor is a general purpose processor. The general purpose processor is used as a host (master) CPU for the N-1 slave processors. In such conventional multiprocessor systems, the N-1 slave processors typically run ROM based code. As a result, the N-1 slave processors have very low observability. Additionally, debugging of the multiprocessor system with ROM based code is a very complicated task, especially when the slave processors do not have special debugging hooks.
It may be desirable to provide (i) improved observability and (ii) improved debugging process in an integrated embedded system.
The present invention concerns an apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) section. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or. (ii) a second mode that processes code stored in the one or more first RAM sections.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing an integrated embedded system that may (i) allow increased observability and decreased debugging complexity of ROM based code, (ii) allow RAM based code debugging to be utilized instead of ROM based debugging, (iii) implement software breakpoints and/or (iv) provide inter operability of processors and memories in multiprocessor embedded systems.